This invention relates to digital signal processing and in particular to an apparatus and method for short cycling sequences of a precision (P) code generator in a signal processor of a Global Positioning System (GPS) receiver.
The Global Positioning System (GPS) is a navigation system based on eighteen satellites in orbit. When fully operational the eighteen satellites will be evenly dispersed in three, inclined, 12-hour circular orbits chosen to ensure continuous 24-hour coverage. The GPS will provide extremely accurate three-dimensional position and velocity information to users anywhere in the world. Normally, four satellites are required for precise location determination in four dimensions (latitude, longitude, altitude and time). The location determinations are based on measurement of the transit time of RF signals from the satellites selected from the total of eighteen. Each satellite transmits a pair of L-band carrier signals, an L1 signal at 1575.42 MHz and on L2 signal at 1227.6 MHz. The L1 and L2 signals are biphased modulated by two pseudo-random noise (PRN) codes; a P-code provides for precision measurement of transit time and a C/A (coarse/acquisition) code provides for a coarse measurement of transit time and provides for easy lock-on to the desired signal suitable for many commercial purposes.
The P-code is the principal navigation pseudo-random noise (PRN) ranging code of the Global Positioning System. The P-code is a repetitive sequence of bits referred to as chips (in spread spectrum parlance). The P-code generator in a NAVSTAR GPS receiver reproduces the P-code that is generated by a P-code generator of a particular NAVSTAR GPS satellite and each satellite produces a unique P-code. However, the design of the P-code generator in a receiver of a user can vary as long as the P-codes generated are the same as those of the satellites. The conventional P-code generator comprises four shift-register stages, each stage including input registers and multiplexing for storing and gating initialization state vector words into the shift registers.
New applications of the GPS system have identified the need for a GPS receiver having a signal processor implemented on a very large scale integrated (VLSI) circuit. In order to accomplish this level of integration, the signal processor has to be designed with minimum circuitry to facilitate getting it on a VLSI circuit chip. The manner in which the invention causes a circuitry reduction in a stage of the P-code generator, resulting in a quadruple reduction per signal processor channel in a portion of the P-code generator, will be understood as this specification proceeds.